ARCHITECTURAL OPTIMIZATION OF AES TRANSFORMATIONS AND KEYEXPANSION


ARCHITECTURAL OPTIMIZATION OF AES TRANSFORMATIONS AND KEYEXPANSION

K. Rahimunnisa1 , M. Priya Zach1 , S. Suresh Kumar2 , J.Jayakumar3

1Department of Electronics and Communication Engineering, Karunya University, Coimbatore, India. 2Department of Electronics and Communication Engineering, Dr. N.G.P Institute of Technology, Coimbatore, India. 3Department of Electrical and Electronics Engineering, Karunya University, Coimbatore, India.

ABSTRACT

Advanced Encryption Standard (AES), is a cryptographic algorithm used for data protection. Designing an efficient hardware architecture for AES with small hardware resource usage is a challenge. Many works are going on for the efficient implementation of AES. The cost and power consumption of the AES can be reduced considerably by optimizing the architecture of AES. AES uses different data transformations such as AddRoundKey, SubByte, ShiftRow and MixColumn transformation and KeyExpansion block. In that, the two expensive transformations in terms of computational resources are MixColumns and SubBytes transformations. In this paper, new techniques for the ASIC implementation of the above transformations and KeyExpansion block are proposed.

KEYWORDS

AES, S-box, LUT, MixColumn ,KeyExpansion

SOURCE URL

https://wireilla.com/papers/ijcis/V2N3/2312ijcis11.pdf

VOLUME LINK

https://wireilla.com/ijcis/vol2.html



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